| Dr. Aly El-Osery |  |
EE 231L: Digital Electronics Lab
(Tentative Schedule)
Grading
| Number | Title | Dates |
| Lab 0 | Wire Wrapping Project: Counter Board | Sep. 3 and 8 |
| Lab 1 | HCMOS Logic Family | Sep. 10 and 15 |
| Lab 2 | Introduction to Verilog HDL and Quartus | Sep. 17 and 22 |
| Lab 3 | Decoders and Multiplexers | Sep. 24 and 29 |
| Lab 4 | 4-Bit Adders/Subtractor | Oct. 1 and 6 |
| Lab 5 | Arithmetic Logic Unit | Oct. 8 and 13 |
| Lab 6 | Debouncing Switches | Oct. 15 and 20 |
| Lab 7 | Sequential Circuits | Oct. 22 and 27 |
| Lab 8 | Registers | Nov. 5 and 10 |
| Lab 9 | Computer Control Unit | Oct. 29 and Nov. 3 |
| Lab 9 | Computer Control Unit | Nov. 5 and 10 |
| Lab 10 | Build a Computer | Nov. 19 and 24 |
| Lab 11 | Control System | Dec. 1 and 3 |
| Lab 12 | Make-up week | Dec. 8 and 10 |