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EE 231 Digital Electronics
- Grading Policy
Lab Schedule:
| Number | Title | Dates |
| Lab 0 | Wire Wrapping Project: Counter Board | Aug 30/Sep 1 |
| Lab 1 | HCMOS Logic Family | Sep 8, 13 |
| Lab 2 | Introduction to Verilog HDL and Quartus | Sep 15, 20 |
| Lab 3 | Decoders and Multiplexers | Sep 22, 27 |
| Lab 4 | 4-Bit Adder/Subtractor | Sep 29/Oct 4 |
| Lab 5 | Arithmetic Logic Unit | Oct 6, 11 |
| Lab 6 | Debouncing Switches | Oct 13, 18 |
| Lab 7 | Sequential Circuits | Oct 20, 25 |
| Lab 8 | Registers | Oct 27/Nov 1 |
| Lab 9 | Computer control Unit | Nov 3, 8 |
| Lab 9 | Computer control Unit | Nov 10, 15 |
| Lab 10 | Build a Computer | Nov 17, 22 |
| Lab 11 | Control System | Nov 29/Dec 1 |
| Make-up week | Dec 6, 8 |