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EE 231 Digital Electronics Lab (Fall 2017)
- Syllabus
- Making an Eight-Bit:Using Verilog and Assembly Coding Styles
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Constants.v
Constants.v (by William Brooks)
Memory contents file required for LAB 9
- mem_init.v Memory file required for LAB 9
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mem_block.v
mem_block.v (by Thomas Dearing)
Lab Schedule:
| Date | Laboratory |
| 8/29 - 8/30 | Lab 0: HCMOS Logic Family |
| 9/5 - 9/6 | Lab 1: Introduction to Verilog HDL and the Altera IDE |
| 9/12 - 9/13 | Lab 2: Decoders and Multiplexers |
| 9/19 - 9/20 | Lab 3: Adder/Subtractor |
| 9/26 - 9/27 | Lab 4: Arithmetic Logic Unit (ALU) |
| 10/3 - 10/4 | ( Lab 4: ) |
| 10/10 - 10/11 | Lab 5: Registers |
| 10/17 - 10/18 | Lab 6: Debouncing Switches |
| 10/24 - 10/25 | Lab 7: Reaction Timer |
| 10/31 - 11/1 | Lab 8: Computer Control Unit... |
| 11/7 - 11/8 | ...Lab 8: Computer Control Unit |
| 11/14 - 11/15 | Lab 9: Build a Computer... |
| 11/21 - 11/22 | ...Lab 9: Build a Computer |
Sample Report by Courtney Johnson
Constants file required for LAB 9