Hector Erives
Associate Professor
EE 231 Digital Electronics
Syllabus

Homework (Fundamentals of Digital Logic with Verilog Design)
Homework #1: 2.6, 2.9, 2.13, 2.19, 2.29, 2.34, 2.53, 2.60, 2.63 (Due 9/6)
Homework #2: 3.2, 3.3, 3.5, 3.9, 3.14, 3.18, 3.21, 3.25 (Due 9/23)
Homework #3: 4.4, 4.7, 4.10, 4.15, 4.17, 4.19, 4.22, 4.25, 4.28 (Due 10/9)
Homework #4: 5.5, 5.7, 5.9, 5.15, 5.17, 5.20, 5.25, 5.27, 5.31 (Due 10/30)
Last Modified: August 2013