EE 231 Digital Electronics Lab (Fall 2018)
LABS
Lab 0: HCMOS Logic Family
Lab 1: Introduction to Verilog and Vivado_ISE
Lab_2_Decoders_Multiplexers_F2018
Lab_3_Adder-Subtractor_F2018
Lab_4_ALU_F2018.pdf
Lab_5_Registers_F2018
Lab_6_Debounced_Switch_F2018
Lab_7_Reaction Timer_F2018
Lab_8_CCU_F2018
Lab_9_Computer
Constants.v
Memory_Block.v
SUPPLEMENTS:
Supplement_Calling_Modules_and_Splitting_Vectors_F2018.pdf
ExtraCredit_Flashing_the_Spartan_7
EE_231L_Final_Formal_Report