In this lab you will design and build two finite state machines (FSM's) based on the digital combinational lock problem discussed previously in class. For your 3-bit digital combination (L2, L1, L0) use the month of your birth mod 8 expressed as a 3 bit binary number (e.g. March => 3 mod 8 = 3 -> 011; September => 9 mod 8 = 1 -> 001).
|
The lock has four inputs (RESET, ENTER, KEY-IN, and CLOCK) and two outputs (UNLOCK and ERROR). The user should reset the machine before entering his/her code. First, set the least significant bit (LSB) of the code using a single-pole double-throw switch to apply the desired value of KEY-IN and then hit the ENTER button (a synchronized and debounced momentary switch), causing the LSB of the code to be read. The remaining two bits of the combination should be applied in the same manner. The UNLOCK signal should be connected to a LED on the protoboard and asserted (high) when the correct 3-bit combination has been supplied. The ERROR signal should also be connected to a LED and should be asserted when an incorrect combination has been applied. |
Note that the combination code is applied serially (and asynchronously) using the KEY-IN switch. The CLOCK signal should be a "high-speed" (>1KHz) TTL clock. The RESET input should be asynchronous and active high. The ENTER signal should be active high, synchronous, and one-clock period wide. To assist you in generating the ENTER signal, as described above, the file sync_switch.tdf has been provided. Make this file a symbol and add it to your overall design. Potential STDs for your designs are provided below. One is a Mealy design and the other a Moore design.
 |
 |
There are several ways to enter state machines using Altera:
Examples of the four methods of implementing Mealy and Moore machines are attached. Design, simulate, build and test the following state machines:
Be sure to print simulation waveforms for all 8-possible input combinations and demonstrate the operation of your lock to the instructor or TA. Note that, you will be using the LPM7064LC44-15 ALTERA chip not the ...7032... part!!
SUBDESIGN moore1
% Design using an excitation table %
(
clk, rst,y : INPUT;
z : OUTPUT;
)
VARIABLE
% state output %
ss: MACHINE OF BITS (z)
WITH STATES (s0 = 0,
s1 = 1,
s2 = 0);
BEGIN
ss.clk = clk;
ss.reset = rst;
TABLE
ss, y => ss;
s0, 0 => s2;
s0, 1 => s1;
s1, 0 => s2;
s1, 1 => s1;
s2, 0 => s1;
s2, 1 => s0;
END TABLE;
END;
|
SUBDESIGN moore2
% Design using CASE statement %
(
clk, rst,y : INPUT;
z : OUTPUT;
)
VARIABLE
ss: MACHINE WITH STATES (s0, s1, s2);
BEGIN
ss.clk = clk;
ss.reset = rst;
CASE ss IS
WHEN s0 =>
z = GND;
IF y == GND THEN
ss = s2;
ELSE
ss = s1;
END IF;
WHEN s1 =>
z = VCC;
IF y == GND THEN
ss = s2;
ELSE
ss = s1;
END IF;
WHEN s2 =>
z = GND;
IF y == GND THEN
ss = s1;
ELSE
ss = s0;
END IF;
END CASE;
END;
|
SUBDESIGN moore3 % Design using D Flip-Flops % ( clk, rst,y : INPUT; z : OUTPUT; ) VARIABLE q2 : DFF; q1 : DFF; BEGIN q2.clk = clk; q2.clrn = !rst; q2.d = !q2 & !y; q1.clk = clk; q1.clrn = !rst; q1.d = (!q2 & y) # (q2 & !q1 & !y); z = q1; END; |
 |
SUBDESIGN mealy1
% Design using an excitation table %
(
clk : INPUT;
rst : INPUT;
y : INPUT;
z : OUTPUT;
)
VARIABLE
ss: MACHINE
WITH STATES (s0, s1, s2);
BEGIN
ss.clk = clk;
ss.reset = rst;
TABLE
% current current next current %
% state input state output %
ss, y => ss, z;
s0, 0 => s2, 0;
s0, 1 => s1, 0;
s1, 0 => s2, 0;
s1, 1 => s1, 1;
s2, 0 => s1, 1;
s2, 1 => s0, 0;
END TABLE;
END;
|
SUBDESIGN mealy2
% Design using CASE statement %
(
clk : INPUT;
rst : INPUT;
y : INPUT;
z : OUTPUT;
)
VARIABLE
ss: MACHINE
WITH STATES (s0, s1, s2);
BEGIN
ss.clk = clk;
ss.reset = rst;
CASE ss IS
WHEN s0 =>
z = GND;
IF y == GND THEN
ss = s2;
ELSE
ss = s1;
END IF;
WHEN s1 =>
z = y;
IF y == GND THEN
ss = s2;
ELSE
ss = s1;
END IF;
WHEN s2 =>
z = !y;
IF y == GND THEN
ss = s1;
ELSE
ss = s0;
END IF;
END CASE;
END;
|
SUBDESIGN mealy3 % Design using D Flip-Flops % ( clk : INPUT; rst : INPUT; y : INPUT; z : OUTPUT; ) VARIABLE q2 : DFF; q1 : DFF; BEGIN q2.clk = clk; q2.clrn = !rst; q2.d = !q2 & !y; q1.clk = clk; q1.clrn = !rst; q1.d = (!q2 & y) # (q2 & !q1 & !y); z = (y & q1) # (!y & q2); END; |
 |