EE 101
Pre-Lab Exercise 8
Do Problem P12.36 from your textbook.
(end of pre-lab)
EE 101
Lab Exercise 8: K-MAP Circuit Reduction and Introduction to Stimulus
Generator and Logic Analyzer
The purpose of this lab is to demonstrate the usefulness of K-MAPs for combinational
logic circuit reduction and to introduce the student to the stimulus generator and logic
analyzer laboratory equipment.
1. Construct a truth table based on the Boolean equation given in Problem P12.36(a)
(from the pre-lab).
2. Draw and fully label a schematic for the Boolean equation given in Problem
P12.36(a). Before you begin drawing, note that the term BC appears several
times in the equation. Use this knowledge to eliminate several gates from a schematic
drawn without considering the BC combination. Include gate identifiers, pin numbers, and
chip designators ("U" numbers) on your schematic. YOU DO NOT HAVE TO BUILD THIS
CIRCUIT!
3. Build the minimized circuit you designed after performing the K-MAP
simplification (from part c of the pre-lab). For every high and low combination of the
inputs, test your circuit by using a logic probe. Construct a truth table showing your
results. This truth table should agree with the truth table you derived from the
unsimplified circuit (from part 1). If they do not agree, find out where the problem is
before proceeding. When finished, turn the protoboard off, but DO NOT DISASSEMBLE YOUR
CIRCUIT YET.
4. You will now hook the stimulus generator and logic analyzer onto your circuit.
Refer to the model setup in the lab when needed.
a. Using one of the ganged cables provided in the lab, attached the ganged end
to the first 8 pins on the stimulus pod (labeled INPUT 0 through INPUT 7) and at
the other end of the cable, attach the first three lines (inputs 0, 1, and 2) to a pin
header in your protoboard. In the holes next to where the pin header is attached, run
three wires to the A, B, and C inputs of your circuit. Let INPUT 0 tie into the C input of
your circuit, INPUT 1 into the B input, and INPUT 2 into the A input.
b. When working with digital circuits, it is extremely important to establish a common
ground between all parts of the circuit and any instruments acting on the circuit.
Otherwise, the circuit simply may not work. On the logic analyzer pod, locate a
ground lead (labeled GND) and plug this into one of the GROUND pins on the stimulus pod.
Again on the logic analyzer pod, find another ground lead. This time, plug it into
a pin header that is placed so it is in contact with the ground on your AND gate chip. A
common ground has now been established between the stimulus pod, logic analyzer, and
circuit.
c. You will now hook the logic analyzer up to the inputs and output of your
circuit. It is an unfortunate, but somewhat unavoidable occurrence that the logic analyzer
lines tend to break. Whenever this happens, we try to put a tag on the logic analyzer pod
indicating which lines do not presently work. Look at the logic analyzer pod for any such
note. The following instructions assume your pod is fully functional. If you have a pod
where any of the first three lines are not working, do not use these lines, but simply use
the next available ones.
Place another pin header alongside the one where A, B, and C tie into your circuit so
that you will have another set of nodes that tie to those inputs.
From the logic analyzer pod, attach line 1 to signal A on the pin header.
Likewise, attach lines 2 and 3 to signals B and C, respectively. Having the three input
stimuli attached to the logic analyzer will enable you to monitor your A, B, and C inputs.
Next, attach line 4 from the logic analyzer pod to a pin header that comes into contact
with the output ("F") of your circuit.
d. Call one of the lab TAs over to look over your wiring.
5. Login to a PC (Windows NT network) and load the logic analyzer software (PA485
on the taskbar, under the Programs menu).
a. Double click on the Field Editor icon. A channel number versus signal name
chart appears. Wherever there is an asterisk, this means that that particular channel
number is mapped to that signal name. For instance, when you first invoked the field
editor, "control" was mapped to channels 41 through 48, "databus" was
mapped to channels 25 through 40, and "addrbus" was mapped to channels 1 through
24. At this time, click the mouse on each asterisk to make them disappear (and thus
destroy the default channel to signal name mapping scheme).
b. Go back to the vertical column where the default signal names are (control,
databus, and addrbus). Go to the first field ("control") and activate it with
the mouse. Press the delete key to remove "control" and then type an
"A" in its place. Similarly, do this to the next three fields and type
"B", "C", and "F" in each one, respectively.
c. Across from where you entered the "A" signal name, click the mouse
under channel 1 so an asterisk appears. In the same way, across from signal B, click under
channel 2. For signal C map channel 3, and for the output F, map channel 4.
d. Under the Edit menu, select clock setup. Change the clock mode (sampling
rate) to 100 KHz.
e. Click on the Internal Trigger Patterns icon to activate a trigger point. You
should see a column for every signal you have defined. Under all your inputs, replace the
"x" with a "0" in the pattrn01 row. Leave the output column, F, as an
"x". The logic analyzer is now configured to begin data collection when it
senses A, B, and C to be zeros.
f. Under the File menu, select Save and then Setup Conditions.
Save the setup conditions you just configured in a file with a .set extension (for
example, lab8.set or 3bit.set).
6. You will now program the PCs stimulus generator to cycle through all
combinations of the A, B, and C inputs.
a. Using your favorite editor, create a stimulus file to count from 0002
to 1112 (see below). This will provide all of the possible input combinations
for your circuit. You can name the file whatever you like, but it must have a .stm
extension (i.e. - 3bit.stm). Your edited file should look like the following.
stimulus =
%000
%001
%010
%011
%100
%101
%110
%111
Note that the % sign indicates binary numbers. The stimulus generator
has the ability to understand binary (prefix = %), octal (prefix = 0), decimal (no
prefix), and hexadecimal
(prefix = $) numbers from stimulus files.
b. Open a 4dos window (if you have not opened one already).
Run your stimulus file by typing "stimulus" followed by the name of the file you
just created (i.e. - stimulus 3bit.stm). If all is well, you should see the stimulus file
you created scroll by. The stimulus is now continuously cycling its outputs from 0002
to 1112 at a default rate of 10 KHz. You can read more about how the stimulus
generator operates in the user instruction manual found in the digital lab.
7. Turn the protoboard on. Go back to the logic analyzer window and
click the mouse on the Go button. If everything is working, the logic analyzer
should trigger (you should hear a beep when the logic analyzer triggers). If your logic
analyzer does not trigger, call for assistance.
If the logic analyzer is working properly, a window with waveforms for the input and
output signals may appear. Or, you may have to maximize the waveform display from icon
form.
Once the waveforms are visible (and each signal is toggling properly -- no flat
liners!), verify the output for each state (from 0002 to 1112) with
the truth table from part 1.
Zoom in or out so that you can read the waveforms easily. Place cursors in the middle
of the 0002 state (for the red line cursor, use the left mouse button) and the
1112 state (for the blue line cursor, use the right mouse button). Zoom out so
that the distance between the red and blue cursors takes up only an eighth or so of the
window. Print out your waveform data and include this in your lab book.
Question:
1. If you would have had to build the circuit prior to K-MAP
reduction, how many two-input AND gates, two-input OR gates, and NOT gates would you have
used? How many total chips would your circuit have needed?