EE 231
Lab 9: T-Bird Taillights Implemented as a Synchronous Counter

1. How many states do we need ?

   
   
   

2. How many bits per state are needed ?

   
   
   

3. Design a synchronous counter, using D Flip-Flops, to generate the above sequence, taking appropriate care with the consecutive 0's. Make sure that, if your system ever enters an unused state, it will return into the desired sequence (i.e., make it self-starting).

   
   
   

4. Design the counter in Altera, using either a .gdf or a .tdf file. Simulate and verify its operation.
   
   
   
   
   
   
   
   
   
   
   
5. OPTIONAL BONUS QUESTION (+10%):
   Design a counter in Altera to use a single input L'/R to have the signal indicate a right turn when L'/R=1 (i.e. ..., 0, 0, 8, 12, 14, 15, ...) and a left turn when L'/R=0 (i.e. ...0, 0, 1, 3, 7, 15, ...).