In the first part of this lab, you will write a simple program to use expanded memory and expanded ports A and B. In the second part of the lab you will look at timing in expanded mode. To do this, you will connect address, data and control lines from your expansion board to the logic analyzer. There is one problem with this - the address and control lines coming out of the Altera chip to the memory chip are not easy to connect to the logic analyzer. In order to be able to look at these lines, you will get rid of expanded ports A and B, and put duplicates of address and control lines onto the headers which were used for these ports.

1. Write a C program which uses the timer overflow interrupt to increment External Port A, and uses the 16 ms real time interrupt to decrement External Port B. In your lkf file, put this program starting at address 0x1000. Connect the four most significant bits of expanded ports A and B to LEDs on your breadboard to verify that your program works.

2. Redo your Altera code from last week. Be sure to keep a copy of your original code so you can reprogram your Altera chip at the end of the lab.
   1. Remove all the parts about the expanded ports. You should just have the hc12_exp.gdf and memexp.gdf files. Edit the hc12_exp.gdf file so only the memory expansion block remains.

   2. In the Assign Pins section, remove the assignments for Expanded Ports A and B. Connect address pins A7-A0 to the eight header pins which were used for EA7-EA0. Connect the control lines CEn, OEn WEn, LBn and A0 (the same as UBn) to the header pins which were used for EB4-0.

3. Connect the logic analyzer to the address line A7-A0, address/data AD15-AD0, and the control lines of your system. The control lines you need to connect are LSTRBn, R/W, and E from the HC12, and CEn, OEn WEn, LBn and A0 from the Altera chip. Note that you can connect to AD15-AD0, LSTRBn, R/W and E by connecting to headers on the top of your HC12 board. Run the following program, which can easily be entered from BUFFALO:

        CODE:      section  .text     
                   org      $1000
   
                   ldd      #$aa55
        loop:      staa     $1020
                   stab     $1021
                   ldd      $1020
                   bra      loop
   

   Running this program the HC12 will do an 8-bit write to an even address ($1020), an 8-bit write to an odd address ($1021), and a 16-bit read from an even address ($1020). In addition, the HC12 will do reads from external memory to fetch the instructions it needs to execute.

   Group things together so you get a timing diagram showing A7-A0 and AD15-AD0 as Hex numbers. Measure the following times, and compare them (where appropriate) to the times in Section 19 of the Motorola M68HC12B Family Manual:

   1. The length of time the E clock is high.
   2. The length of time the E clock is low.
   3. The read/write delay time - the length of time from E going low to R/W going low on a write cycle.
   4. The address delay time - the length of time from E going low to a new address on AD15-0.
   5. The adress latch time in the Altera chip - The length of time from E going high until a new address appears on A7-0.
   6. The length of time OEn, WEn, and CEn are low.
   7. The length of time from E going high to CEn going low.
   8. The length of time from E going low to CEn going high.
   9. The address hold time - the time from E going high to AD15-0 changing from address mode to data mode.
   10. The HC12 data hold time - the time from E going low to AD15-0 changing from data to address mode during a write cycle.
   11. The RAM access time - the time from CEn going low the the RAM chip putting data on the data bus on a read cycle.
   12. The RAM data hold time - the time from CEn going high to the RAM chip releasing the data bus.

   Note that, because of the clock speed of the logic analyzer, you will not be able to measure very short times.

4. Reprogram your Altera chip to restore your Expanded Ports A and B.