EE 308
Exam 3
Solutions
A15 A14 A13 = 1 1 1 A12 = 0 A11 A10 R/W = 0 1 0 Addr = 1110 01XX XXXX XXXX, R/W = 0 Addr = 0xE400 - 0xE7FF Output
A15 A14 A13 = 1 1 1 A12 = 0 A11 A10 R/W = 1 0 1 Addr = 1110 10XX XXXX XXXX, R/W = 1 Addr = 0xE800 - 0xEBFF Input
#define
statement which will access data in
a peripheral connected to output Y5:
#define EXP_Y5 (* (unsigned char *) 0xE800)
A15 A14 A13 = 1 0 0 A10 A11 A12 = 0 1 0 Addr = 1000 10XX XXXX XXXX Addr = 0x8800 - 0x8BFF
From Figure A-14 of the Technical Data Manual, corresponding time is 3 - 19, or 222 ns - 128 ns = 94 ns. HC11 puts data on bus 94 ns before E goes high, STUPID needs it 80 ns before, so time is compatible.
From Figure A-14 of the Technical Data Manual, corresponding time is 21 - 9, or 33 ns - 33 ns = 0 ns. HC11 removes data and address at same time, STUPID needs address on 50 ns after data removed, so time is not compatible.
From Figure A-14 of the Technical Data Manual, corresponding time is 12, or 94 ns. HC11 puts address on bus 94 ns before E goes high, STUPID needs address on 140 ns before E goes high, so time is not compatible.
From Figure A-14 of the Technical Data Manual, corresponding time is 9, or 33 ns. HC11 holds address on bus 33 ns after E goes low, STUPID needs address on held for 20 ns before E goes low, so time is compatible.
This is the amount of time STUPID needs valid data on bus before E goes low.
Read the port for which the flag is set. For example, if IRQA1 is set, read EXP_PORTA.
EXP_CRB = 0x00; /* Access DDRB */ EXP_DDRB = 0xff; /* Make Port B output */ EXP_CRB = 0x2c; /* CB2 control = 101; DDRB access = 1; CB1 control = 00 */
EXP_CRA = 0x00; /* Access DDRA */ EXP_DDRA = 0x00; /* Make Port A input */ EXP_CRA = 0x2d; /* CA2 control = 101; DDRA access = 1; CA1 control = 01 */
temp = EXP_PORTB; /* Make sure flag clear by reading port */ EXP_PORTB = data; /* Write data to port */ while ((CRB & 0x80) == 0) ; /* Wait for acknowledgement */
Read SPSR, then read from or write to SPDR.
DDRD |= 0x38; /* SS, SCK, MOSI outputs; must do this before setting up */ /* SPCR */ SPCR = 0x56; /* SPE = 1, MSTR = 1 */ /* CPHA = 1 -- Data stable on 2nd clock edge */ /* CPOL = 0 -- latch data on falling edge */ /* SPR[1:0] = 10 -- 125 kHz clock (fastest compatible with */ /* SOTC-001 */
PORTD |= 0x20; /* Select SOTC-001 */ temp = SPSR; /* First step in clearing SPIF */ SPDR = 198; /* Writes to SOTC-001 and finishes clearing SPIF */ while ((SPSR & 0x80) == 0) ; /* Wait for transfer to finish */ SPDR = 0x00; /* Write dummy byte to SOTC-001 to get SCK going; */ /* Also clears SPIF */ while ((SPSR & 0x80) == 0) ; /* Wait for transfer to finish */ oven_temp = SPDR; /* Read oven temperature from SOTC-001 */ PORTD &= ~0x20; /* Deselect SOTC-001 */