| SUMMARY OF HC11 TIMER SUBSYSTEMS | ||||||||||
| Interrupt | TOF | RTI | Input Capture | Output Compare | Output Compare | |||||
| 1-4 | 2-5 | 1 | ||||||||
| Prescaler | Rate | Edge to Capture | Action when TCNT = TOCx | Bits of Port A to Control | ||||||
| PR Bits in TMSK2 | RTR Bits in PACTL | EDGx B:A in TCTL2 | OMx OLx in TCTL1 | and Action when TCNT = TOC1 | ||||||
| Must set in first 64 cycles | (Time of edge => TICx) | OC1Mx Bit of OC1M | ||||||||
| PR 1:0 | 8 MHz XTAL | RTR 1:0 | 8 MHz | EDGx B:A | EDGE | OMx OLX | Action | 0 | OC1 Not Active | |
| Setup | 0 0 | 32.77 ms | 0 0 | 4.096 ms | 0 0 | Disable | 0 0 | Disconnected | 1 | OC1 Controls PAx |
| 0 1 | 131.1 ms | 0 1 | 8.192 ms | 0 1 | Rising | 0 1 | Toggle OCx | OC1Dx Bit of OC1D | ||
| 1 0 | 262.1 ms | 1 0 | 16.384 ms | 1 0 | Falling | 1 0 | Clear OCx | 0 | Clear PAx | |
| 1 1 | 524.3 ms | 1 1 | 32.768 ms | 1 1 | Any | 1 1 | Set OCx | 1 | Set PAx | |
| Flag | TOF | RTIF | ICxF | OCxF | OC1F | |||||
| Bit 7 of TFLG2 | Bit 6 of TFLG2 | Bits in TFLG1 | Bits in TFLG1 | Bit 7 of TFLG1 | ||||||
| Enable | TOI | RTII | ICxI | OCxI | OC1I | |||||
| Bit | Bit 7 of TMSK2 | Bit 6 of TMSK2 | Bits in TMSK1 | Bits in TMSK1 | Bit 7 of TMSK1 | |||||
| Notes: IC4 and OC5 are both on Bit 3 of Port A. | ||||||||||
| To set up PA3 as IC4, write a 1 to Bit 2 of PACTL. To set up PA3 as OC5, write a 0 to Bit 2 of PACTL. | ||||||||||
| You can force an Output Compare action to occur on pin OCx before TCNT = TOCx by writing a 1 to bit FOCx of the CFORC register. | ||||||||||
| For example, if OC2 is set up to be cleared (OM2 OL2 = 1 0), writing a one to FOC2 (Bit 6 of CFORC) will force OC2 low. | ||||||||||