EE 451
Lab 1: Introduction to the Motorola 56002 EVM
Read Chapters 1 through 3 of the Motorola 56000 DSP Family Manual. There will probably be things you don't understand, but don't worry about this. Just try to get a flavor of how the chip operates.
The Motorola 56002 is a microcontroller optimized for performing digital signal processing operations. The heart of the 56002 is a 56000 CPU core. This core CPU has a 24-bit data path and a 16-bit address path. The basic operation in digital signal processing is solving a difference equation:
M N -- -- y[n] = \ b x[n-k] - \ a y[n-k] / k / k -- -- k=0 k=1
A DSP chip has to multiply two numbers (usually, a coefficient and a data value) and add the result to a running sum as quickly as possible. The 56000 can do these two operations in a single instruction, called a multiply-and-accumulate (mnemonic: MAC). In addition to the MAC operation, the CPU must efficiently retrieve the next coefficients and data from memory to prepare for the next MAC. On the 56000, these memory fetches can be done in the same instruction as the MAC. On a standard CPU, the entire MAC operation might look like this:
mpy x0,y0,b ; multiply regs x0 and y0; result to reg b add b,a ; accumulate reg b to reg a move (r0),x0 ; put coef pointed to by reg r0 into reg x0 move (r4),y0 ; put data pointed to by reg r4 into reg y0 inc r0 ; update reg r0 to point to next coef inc r4 ; update reg r4 to point to next data
The same thing can be done on the 56000 with the following single instruction:
mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0
The 56002 we use in the lab can do 20 million MACs per second. Faster versions of the Motorola chip can do 80 million MACs per second. In addition to being optimized for performing this MAC instruction, the 56000 has several other optimizations which make it far faster for executing DSP algorithms than a standard CPU is.
The 56002 has the 56000 core CPU plus a number of built-in peripherals -- two serial ports, an 8-bit parallel port for interfacing with a host computer (such as a PC), and a 24-bit timer-counter. The 56002 EVM consists of a 56002 DSP chip with a 16-bit 48 kHz stereo codec (dual A/D and D/A converters connected to the 56002 through a serial port).
In the course, we will use the 56002 EVM to illustrate several signal processing algorithms. We will learn enough of the 56000 assembly language to understand how filters, ffts, etc., are implemented, but we won't have to write these routines ourselves -- a library of optimized and debugged routines already exists. Rather, we will package these routines into programs to process audio-frequency signals.
This write-up will give an outline of things to do to become familiar with the 56002 EVM and its software interface. Details will be supplied in a brief lecture at the beginning of the laboratory session.
move x0,a add y0,a move a,x:0
;************************************************************************** org y:$0 coef dc 0.125 result ds 1 ;************************************************************************** org x:$0 data dc 0.5 ;************************************************************************** org p:$40 move y:coef,x0 move x:data,a add x0,a move a,y:result jmp *
asm56000 -a -b -l prog.asm