Your assignment in this lab exercise is to use a programmable logic device (PLD) to implement a combinational logic circuit. The circuit you will program into the Altera EPM7032 EPLD is a simple majority circuit. For this circuit, the output will be high if a majority (two or more) of its inputs are high. For this lab, the AHDL (Altera Hardware Description Language) file that you would normally be responsible for writing has been provided for you below. The purpose of this exercise is merely to familiarize you with the Altera PLD programming software.

 A sample AHDL program, below, implements the majority circuit. The truth table for this circuit is shown in Figure 2. The canonical sum of products expression for the majority circuit is F = !ABC + A!BC + AB!C + ABC. Note that we did not reduce the equation before writing the Altera text design file below. The Max+plus II software does this automatically.
 
 

  Getting started with the Altera Program

1. Log in to a PC.
2. Create a new directory in your U: drive for today's lab
3. Start up the Quartus software, which is what we will use to program your PLD.

Create your design project.

1. Open the project wizard File: New Project Wizard.
   1. Click next after reading the wizard introduction screen.
   2. Page 1: "Directory, Name, Top level Entity"
      1. For your "working directory" use the ".." button to select the directory you just created for today's lab. Click Open.
      2. Name your circuit by typing "majority" in the project name text box. (Top level design entity is automatically filled in.
      3. Click Next
   3. Page 2: "add files" screen is not needed now. Click next
   4. Page 3: Family and Device Settings screen:
      1. From the Family pulldown menu, select MAX7000S
      2. From Package pulldown menu, select PLCC
      3. In the Available Devices menu, select EPM7064SLC44-10
      4. Click "Finish" to close the wizard. A project has been created but it does not have any files in it.

2. Create your AHDL text design file:
   1. File: New.   Select AHDL and click ok. The new file you have created is what you will use to write your program.
   2. Enter the program from Figure 1, exactly as you see it, into the text editor.
   3. Save the file. The default file name will match your project name, and the default directory is the location of your project. Use these defaults.

3. Compile the project
   1. On the toolbar, click the purple play button. This compiles the program and opens a new document tab for the compilation results.
   2. If problems are reported, troubleshoot your program and try again until you get the "Full compilation was successful" message.

4. Create a timing diagram to run your simulation:
   1. File:New
   2. Select the "Verification/Debug Files" tab
   3. Select "Vector Waveform File" and click OK. This opens a timing diagram window
   4. Edit: "Insert Node or Bus" (or double click in the white part of the "Name" panel). This opens the Node/Bus window
      1. Click "Node Finder" button (opens the Node Finder window)
      2. Click on "List" button. The inputs and outputs you defined in your program should now be listed in the "Nodes Found" panel. If they do not show up, find the the Filters drop-down box and be sure that Pins: all is selected.
      3. Use the arrow buttons to copy them to the "Selected" panel
      4. Click ok here, then again in the Node/Bus window.
   5. Timing settings:
      1. Edit: End time. Enter 8 us and click OK.
      2. View: "Fit in Window" This zooms your eitire timeline into the visible panel.
      3. Establish input conditions so the simulation has hypothetical inputs to act upon. This should make the inputs for your timing diagram look like the input conditions we theorized in the prelab lecture.
         1. Click on the A node in the "Name" panel. This is the most significant bit.
         2. We need to overwrite this waveform with a clock signal to simulate the periodic inversion of this signal. Click on the clock icon button and use the following settings:
            Start time = 0, End time = 8us, Period = 8us, Offset = 0, Duty cycle = 50%. Click OK.
         3. Click on the B node, click the clock icon, all settings are the same for the A node except Period = 4us.
         4. Repeat for the C node using Period = 2us.
      4. Save your VWF file (again, use the default name and directory).

5. Simulate your program
   1. Processing: "Start Simulation" (or use the blue ~play button).
   2. A new "Simulation" tab will open and you should now see the F node displays the output waveform. To see the whole duration of the simulation use View: Fit in Window like you did in the timing diagram.
      * If a new window doesn't open to show the simulation (existing window still shows your original timing diagram with a row of "XXXXXX" for your F output), we need to change a setting in the program. In the Processing menu, select Simulation Debug and from the submenu select Last Simulation Vector Outputs. This will now display the simulation results window.
   3. Observe how the inputs determine the output. Check your majority circuit truth table to confirm that each row (which corresponds to each 1 us block on the timing diagram) generates the correct F output. If it does not output correctly, go back to your program TDF and be sure your truth table was entered properly. If not, fix it, re-compile, and re-simulate.
   4. Print a copy of the simulation to put in your lab book. File: Print (or use the printer toolbar button). Use the default settings and click ok.
   5. Now that we know we have a working program, go back to the majority.tdf file to print a copy of the text design file for your program. Put it in your lab book.

6. Print a pin-out diagram.
   1. File: Open. Select "All file types" and double click on "majority.pin".
   2. Scroll down until you see a Pin Name/Usage/Location table which specifies how to connect your device.
   3. Use the cursor to select all the rows of the table.
   4. Print the pinout table. File:Print, choose "Selection" for the print range (be sure to do this or it will waste several pages printing the entire report document). To keep the printout small, use the print properties button and select to print two pages per sheet.

Install the Program on your PLD chip

1. Go to the programming station to the right of the printer.
2. Insert your Altera chip into the programming adaptor. Be sure it is oriented properly according to the diagram on the adaptor module. Close the cover so that it clicks shut.
3. Log in to the computer and into your network account. (If someone else is already loged in, log them out first).
4. Open the Altera MAX Plus II software, it's a red desktop icon. (Do not open Quartus)
5. From the File menu choose File:Project:Name
6. Select your file from the list (either of the files with the "majority" name will work). After you click ok it looks like nothing happened on your screen--that's ok, it's just loaded your project without opening any of its files.
7. From the MAX+PlusII menu, choose Programmer.
8. Click the "Program" button
9. When it has finished programming your chip you may open the socket and remove your it.
10. Log out of the computer (logging out of the computer automatically closes all programs and logs you off the network).

1. Take your chip back to your workstation and install it in the PLCC adapter board.
   • Note that certain pins are always going to be tied to Vcc and GND. For the EPM7064, pins 3, 15, 23 and 35 are always tied to Vcc, and pins 10, 22, 30 and 42 are always tied to ground. Those pins always tied to ground are labeled GND, additional ground connections that you need to make are labeled GND- or GND+, the same applies to Vcc. We have designed the adapter board to tie the permanent Vcc and ground pins together. For those, all you need to do is to connect a single wire from the VCC port on the adapter to +5 volts on the protoboard, and another wire from GND on the adapter to ground on the protoboard. Note (from the printout of your chip) that there are additional grounds and Vcc's that you will still need to hook up. These pin assignments will vary from project to project.
   • Take care that your chip has the proper orientation, and let a lab assistant witness you plugging the chip into its socket.
   • Make sure all GND and Vcc wires are hooked up properly to the device.

2. Wire up your counter (74HC4040) as described in the pre-lab lecture and your programmed Altera chip.
   • The outputs of the counter chip will be hooked up as inputs to the Altera chip.
   • The "clock" input of the counter chip will be driven by the clock on the protoboard. The clock will cycle through all possible inputs for your Altera chip, saving you from having to wire each combination of the inputs by hand for testing.

3. Use the logic probe to test the output of your circuit by sampling the F output from your Altera chip.
   • If you slow the protoboard clock enough so that you can hear the transitions, you should be able to match the lights and tones to the timing diagram output "song" you expected.
   • If it does not work as expected, confirm that your simulation generated correct results.
     • If it did not, you will need to fix your program and re-install it on your chip.
     • If it did, check your wiring. A common mistake is to reverse the order of bits - be sure you have correctly interpreted which are the most and least significant bits. Check the rest of your wiring, being careful to follow the altera diagram closely. Make sure all Vcc and GND connections are correct. Move methodically through your wiring so that you check everything in an orderly fashion.

4. Call one of the lab TA's over to look over your wiring and confirm your working circuit. TA sign here _______

Using the Logic Analyzer to test your circuit

1. Now you need to use a logic analyzer to visually confirm the timing diagram for your circuit. Take your chip out of the socket and bring it to the protoboard connected to the logic analyzer testing station.

2. It is best to obtain software instructions from the Instructor or TA. Have them help you through this process.
   1. Plug your chip into the socket in the testing station. The testing unit should already be connected to the logic analyzer. If not, follow these instrutions:
      • From the logic analyzer pod, attach line 0 on the pin header to signal A on your circuit. Likewise, attach lines 1 and 2 to signals B and C, respectively. Having the three input stimuli attached to the logic analyzer will enable you to monitor your A, B, and C inputs.
      • Next, attach line 3 from the logic analyzer pod to a pin header that comes into contact with the output ("F") of your circuit.

   2. Note: When working with digital circuits, it is extremely important to establish a common ground between all parts of the circuit and any instruments acting on the circuit. Otherwise, the circuit simply may not work. On the logic analyzer pod, locate a ground lead (the black wires with green heat shrink) and connect this into a GROUND on the rotoboard. This establishes a common ground between your circuit and the logic analyzer.

   3. Login to the PC that your logic analyzer is connected to (log into windows only, you do not need to log into the network). Open the logic analyzer software called LA Viewer. There should be an icon on the desktop, or you can find it in the start menu.

   4. To be sure you haven't damaged your wiring while moving and attaching it to the logic analyzer, use the logic probe again to confirm that your output F is still working.
      • In LA Viewer you will see 16 channels on the left (0-15) where each one corresponds to a colored wire coming out of the logic analyzer. In our case, we are only using 4 channels (Ch-0...Ch-03) for A, B, C, and F. We should get rid of all remaining channels by holding control to select multiple channels with the mouse, highlight all channels except the ones we are using. Press delete or right-click on the selected and choose 'delete label'.
      • To the upper right of the program you will see a clcok speed in Hertz, this is how fast the program is going to sample the input, so you want this speed to be much faster than the protoboard clock. A good speed for each is 10kHz for the function generator and 5MHz for LA viewer.
      • When the clock speeds are set at the desired values, acquire the signal by clicking the "man running" icon. Your data should appear on the screen. Depending on your clock speeds, you may need to zoom in or zoom out (using the magnifying glass) to clearly see about two cycles through the truth table combinations on A, B and C. An easy way to check your values is to slide the blue marker at the top of the window over a transition period of the timing diagram and check to make sure that the blue numbers on the left match your truth table.

   5. When you are finished with the logic analyzer timing diagram, print a copy for your lab book. The simplest way to do this is to print an application screen shot.
      • Unmaximize the application window.
      • Using the corner drag tool, resize the application window such that it shows only the portion of the window we need (including your signal lines with minimal blank space below).
      • Hold 'Alt' and press 'Print Screen'. This places a screenshot of the application window on the clipboard.
      • Use Open Office to open a text document and paste the image into the document (ctrl-v works to paste).
      • Print the document.

3. Paste the waveform printout into your lab book and describe the results.