Subsections

• 3.2.1 always and reg
• 3.2.2 if-else Statements
• 3.2.3 case Statements

3.2 Verilog - Behavioral Modeling

3.2.1 always and reg

1. Behavioral modeling use the keyword always.
2. Target output is of type reg. Unlike a wire, reg is updated only when a new value is assigned. In other words, it is not continuously updated as wire data types.
3. always may be followed by an event control expression.
4. always is followed by the symbol $@$ followed by a list of variables. Each time there is a change in those variables, the always block is executed.
5. There is no semicolon at the end of the always block.
6. The list of variables are separated by logical operator or and not bitwise OR operator ''|''.
7. Below is an example of an always block.
   
   
   

3.2.2 if-else Statements

if-else statements provide means for a conditional output based on the arguments of the if statement.

3.2.3 case Statements

case Statements provide an easy way to represent a multi-branch conditional statement.

1. The first statement that makes a match is executed.
2. Unspecified bit patterns could be treated using default keyword.