Subsections

• 3.1 Verilog

3 Supplementary Material

3.1 Verilog

3.1.1 Parameters

Parameters are constants and not variables.

parameter num = 8;

3.1.2 Operators

3.1.2.1 ?:Construct

assign y = sel?a:b;

If sel is true, then y is assigned a, else it is assigned b.

3.1.2.2 Concatenations

In Verilog it is possible to concatenate bits using $\{\cdot\}$ .

$\{$ a, b, c, a, b, c$\}$

is equivalent to

$\{2\{$ a, b, c$\}\}$

3.1.2.3 Comparison Operators

assign y = a>b?a:b;

assign y to a if a>b and assign it to b otherwise. Table 2 shows a list of comparison operators.

Table 2: Comparison Operators

Operator	Description
$>$	greater than
$<$	less than
$>=$	greater than or equal to
$<=$	less than or equal to
$==$	equality
$===$	equality including x and z
$!=$	inequality
$!==$	inequality including x and z

• for $==$ and $!=$ the result is x, if either operand contains an x or z.

3.1.2.4 Logical Operators

Table 3 shows a list of logical operators.

Table 3: Logical Operators

Operator	Description
$!$	logical negation
$\&\&$	logical AND
$\vert\vert$	logical OR

• Evaluation is performed left to right.
• x if any of the operands has unknown x bits.

3.1.2.5 Binary Arithmetic Operators

Table 4 shows a list of arithmetic operators.

Table 4: Arithmetic Operators

Operator	Description
$+$	addition
$-$	subtraction
$*$	multiplication
$/$	division (truncates any fractional part)
$\%$	equality

3.1.2.6 Unary Arithmetic Operators

Table 5 shows a list of unary arithmetic operators.

Table 5: Unary Arithmetic Operators

Operator	Description
$-$	Change the sign of the operand

3.1.2.7 Bitwise Operators

Table 6 shows a list of bitwise operators.

Table 6: Bitwise Operators

Operator	Description
$\sim$	Bitwise negation
$\&$	Bitwise AND
$\vert$	Bitwise OR
$\sim\&$	Bitwise NAND
$\sim \vert$	Bitwise OR
$\sim ^\wedge$ or $^\wedge\sim$ Equivalence

3.1.2.8 Unary Reduction Operators

Table 7 shows a list of unary reduction operators. They produce a single bit result by applying the operator to all of the pits of the operand.

Table 7: Unary Reduction Operators

Operator	Description
$\sim$	Bitwise negation
$\&$	Bitwise AND
$\vert$	Bitwise OR
$\sim\&$	Bitwise NAND
$\sim \vert$	Bitwise OR
$\sim ^\wedge$ or $^\wedge\sim$ Equivalence

3.1.2.9 Shift Operators

Table 8 shows a list of shift operators.

Table 8: Shift Operators

Operator	Description
$<<$	left shift
$>>$	right shift

• Left operand is shifted by the number of bit positions given by the right operand.
• Zeros are used to fill vacated bit positions.

3.1.2.10 Operator Precedence Rule

Table 9 shows a list operator precedence rules.

Table 9: Precedence Rules

!,$\sim$	Highest Precedence
$*,/,\%$
$+,-$
$<<,>>$
$<,<=,>,>=$
$== ,!=,===,!==$
$\&$
$^\wedge$ , $^\wedge\sim$
$\vert$
$\&\&$
$\vert\vert$
$?:$	Lowest Precedence

3.1.3 8-bit Adder

Program 1 shows how to implement an 8-bit adder.